ASIC Design Engineer
Vorticity Inc.
Date: 3 weeks ago
City: Redwood City, CA
Salary:
$120,000
-
$190,000
per year
Contract type: Full time
The Role
- Design and develop high-performance, synthesizable RTL code using Verilog or VHDL
- Participate in microarchitecture definition and refinement
- Implement and optimize logic for specific functionalities and performance targets
- Conduct functional verification through simulations and formal methods
- Collaborate with architects, verification engineers, and physical designers to ensure successful integration and production
- Write clear and concise technical documentation
- Stay up-to-date with the latest advancements in digital design technologies and methodologies
- Bachelor's degree in Computer Science, Electrical Engineering, or a related field
- Minimum 2+ years of experience in RTL design and verification
- Proven expertise in Verilog or VHDL
- Understanding of digital logic design principles (combinational circuits, sequential circuits, state machines)
- Familiarity with synthesis and timing constraints
- Excellent written and verbal communication skills
- Strong ability to work independently and as part of a team
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